In most integrated circuit design processes, a circuit designer uses a computer program to develop a logical description of the various components that are to be in a new circuit. Other computer programs then take the logical description and convert it into a description of the individual circuit building blocks that will perform the desired circuit functions. Additional computer programs are then used to convert the description of the building blocks into a layout file that specifies the shapes of the various mask or reticle features that are used to expose a wafer during a photolithographic process in order to form the different layers of the integrated circuit.
As the size of the layout features become smaller than the wavelength of light used to expose the mask or reticle, optical and other process distortions can occur such that the pattern of features that is actually created on a wafer does not match the desired layout pattern. To correct for these distortions, various resolution enhancement techniques (RETs) such as optical and process correction (OPC), sub-resolution assist features (SRAFs), phase shifters etc. can be used to improve the fidelity with which a pattern of features is printed in a wafer.
To use a resolution enhancement technique, a simulation is performed that predicts how the features on a mask or reticle will print on a wafer under defined process conditions. From the results of the simulation, the various RETs are employed to compensate for the expected distortions. As will be appreciated, the ability of a resolution enhancement technique to improve the printing fidelity is closely tied to how well the photolithographic model predicts how the features will print on the wafer. The technology disclosed herein relates to quantifying how well a photolithographic model can simulate a photolithographic printing process.